FPGAs enable flexible network gateway design

With the introduction of wireless field-side standards, such as WirelessHART and current efforts in SP100.11a standardization, gateway implementers are faced with making difficult tradeoffs between the robustness of any wireless solution being offered and the battery life of wirelessly-enabled sensors in the field. With more of the intelligence of the network being absorbed by the network manager/gateway function, gateway designers need reliable, proven solutions as building blocks for successful implementation.

Field programmable gate arrays (FPGAs) offer robust solutions addressing these needs. Vendors provide devices, embedded processors, intellectual property (IP), and complete protocol stacks for plant network protocols, enabling an end-to-end solution for companies wanting to implement various industrial applications.

FPGA benefits include:

Cost reduction — supports many product variants from one base hardware design;

Flexibility — FPGA can be quickly reprogramming for new features or increased performance; and

Protection from obsolescence — same hardware can be used for many customers.

System block diagram

A basic network manager/gateway system contains field-side radio modules for wireless communication, a core system processor, and a communication coprocessor implemented in a low-cost FPGA with an embedded processor. An FPGA offload the task of communication over the plant network, freeing the system processor to handle other core tasks such as managing the network. Implementing the protocol stack in an FPGA allows a single hardware design to support multiple plant protocols. This minimizes inventory costs, because users only have to stock a single gateway variant to support any plant connectivity required.

Engineering a solution to support multiple protocols is clearly possible by developing a series of plug-in boards, one for each protocol, but the number of standards and their constant evolution makes stocking such boards cost-prohibitive. Where standard Ethernet hardware is used, developing or porting protocol software to run on a chosen processor is required. This takes time, and the CPU must have adequate processing power to run the application and protocol.

This basic system contains field-side radio modules for wireless communication, a core system processor, and a communication coprocessor implemented in an FPGA with an embedded processor.

When new Industrial Ethernet chips (ASICs or ASSPs) are required, creating new circuit boards requires new hardware implementations. New hardware means supporting multiple versions of a board as each protocol is upgraded, and facing potential obsolescence of the ASIC or ASSP. This type of solution is likely to be expensive, difficult to support, and slow to deliver new features.

These problems can be solved, however, by implementing an Industrial Ethernet interface in an FPGA. One of the key FPGA benefits is reconfigureability; build one circuit board and program in the hardware required for any Industrial Ethernet protocol at any time, even before the product ships. If a different protocol is needed, or if customers order changes, an FPGA can be easily reprogrammed with a new FPGA configuration file. This type of multi-standard solution can greatly reduce development costs while minimizing inventory and supply chain issues. New software or hardware may need to be developed to create a new configuration file for an FPGA, but this can be easily accomplished. It takes only a few weeks of development time when specific FPGA development tools and off-the-shelf IP from development partners are used.

FPGA-based industrial Ethernet

An FPGA can perform all the functions required by an Ethernet interface. The physical (layer 1) PHY functions and media access controller (layer 2) MAC functions are dealt with by the configured logic in the FPGA. The higher level functions (layer 3 upwards) can be carried out by software running on a processor core designed into the FPGA. Implementing a communication channel between the existing application processor and an FPGA is accomplished through FPGA logic programming, the multi-standard support of the I/O pins, and the availability of a wide range of off-the-shelf interface IP.

Generally, it is possible to use an existing communication facility in a soft processor (such as I2C, SPI or some other local parallel bus) or system (such as PCI, PCI Express or CANopen) to communicate with an FPGA. This approach requires minimal computing time and few changes to the application software running on the existing application processor. It also preserves system software status and delivers additional processor resources for high performance Industrial Ethernet stack processing.

FPGA programmability makes it easy to develop a system that contains two or more soft microprocessor cores and enables integrating the application layer into the FPGA. This type of system integration reduces the overall component count, cost, and power consumption. Additionally, the design is now entirely IP-based, providing protection against obsolescence and the ability to easily migrate the design into newer generations of FPGAs.

Implementation in FPGAs also provides the opportunity to hardware accelerate the system. This generally involves implementing computationally intense functions in FPGA hardware instead of software. The resulting system has higher performance, lower clock speed, and lower power consumption. For Industrial Ethernet, an FPGA hardware design can also include a hub or similar hardware that accelerates the Ethernet communication.

Not only can an FPGA allow off-loading application tasks to a processor or hardware implemented in FPGA logic, but FPGA flexibility allows implementing new interfaces in the system, from simple communication interfaces, to more complex features like support for new memory (such as DDR3), or the latest communication technologies (such as Bluetooth and PCI Express).

There are several other advantages to implementing the Ethernet protocol stack in an FPGA. First, the life of an FPGA typically extends beyond 10 years. Second, latency associated with the processor can be streamlined by implementing slower code in the FPGA logic to speed up interrupts and reduce delay in the system by up to one or two orders of magnitude. This powerful capability is not offered by any other solution.

An FPGA can perform all the functions required by an Ethernet interface.ration.

FPGA design flow

FPGA configuration files are generated by FPGA design and synthesis tools. These tools deliver all the necessary functionality to design, modify, and generate FPGA configurations, and enable a design using VHDL, Verilog, schematic, graphical or block-based design methodologies. Such a design environment offers much higher levels of productivity and supports important development features, such as interfaces to hardware simulation tools, hardware run-time debug tools, and system performance and power optimization capabilities.

Creating a processor and Ethernet MAC hardware design may sound difficult, but in fact it is a relatively straightforward task. Many FPGA vendors offer off-the-shelf IP and design tools that enable easy “plug-and-play” Ethernet MAC and processor functions. FPGA design flows have matured to include fully-tested cores complete with verification suites that can be plugged into a design, and verified as a total system.

FPGAs and soft microprocessor IP has enabled a robust programmable solution for Industrial Ethernet coprocessing. FPGAs deliver support for any Ethernet-based industrial communication protocol from the same base hardware, as well as the benefits of system integration, flexibility, and obsolescence protection that come with programmable logic devices.

Various members of the technical staff in the Industrial/Broadbase business unit of Altera Corporation contributed to this article.

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Building an FPGA-based hardware design

A field-programmable gate array (FPGA) can perform all the functions required by an Ethernet interface or gateway. The physical (layer 1) PHY functions and media access controller (layer 2) MAC functions are dealt with by the configured logic in the FPGA. The higher level functions (layer 3 upwards) can be carried out by software running on a processor core that has also been placed into an FPGA logic configuration. Implementing a communication channel between the existing application processor and an FPGA is accomplished through FPGA logic programming, the multi-standard support of the I/O pins, and the availability of a wide range of off-the-shelf interface IP.

Creating a processor and Ethernet MAC hardware design may sound difficult, but in fact it is a relatively straightforward task. Many FPGA vendors offer off-the-shelf IP and design tools that enable easy “plug-and-play” Ethernet MAC and processor functions. FPGA design tools include fully-tested cores complete with verification suites that can be plugged into a design and verified as a total system.

In some cases, “plug-and-play” IP tools allow the user to connect different functions with a graphical user interface (GUI)-driven tool. Such tools identify the components being connected and can generate HDL code for an entire system-on-a-chip solution with the push of a button. These powerful tools and IP flows enable a designer to take a processor and add any set of peripherals that are needed to interconnect with the outside world.

For example, in addition to the Ethernet MAC, a user can select an RS485 interface or an I2C interface. This “off-the-shelf” approach saves development time and effort, while building a processor that minimizes costs by not having extraneous, unused peripherals take up valuable silicon real estate.

One of the most important components of an embedded system is the processor. In Industrial Ethernet protocols, the processor is required to provide higher layer functions such as TCP, UDP, etc. With an embedded processor and development software, it is easy to create processor-based systems that include Ethernet MAC IP and/or a range of other peripheral components. For example, you can create a system that interfaces to an external processor, and build variants that use different Ethernet MACs to support different Industrial Ethernet protocols, different interfaces for external modules, or even systems with multiple embedded processors for application processing.

A typical FPGA design flow offers much higher levels of productivity, and supports important development features, such as system performance and power optimization capabilities.

An FPGA IP model

FPGA vendors tend to partner with third-party IP providers to offer support for various Industrial Ethernet protocols, software protocol stacks, and other processor peripherals. Support models vary from vendor to vendor. A modular approach might provide individual pieces of the solution, such as the software protocol stack as one module and the Ethernet MAC as a separate module. In this model, the designer is responsible for integrating the modules using the FPGA vendor’s tools.

Another approach is more like a turn-key solution, with complete protocol stacks and an FPGA design offered as a configuration image. This enables a simple-to-use FPGA device that is as easy to use as an off-the-shelf ASIC or ASSP. In both models API libraries are included with C code that provides the interface to call an FPGA protocol stack from the host embedded processor.

Many vendors also provide FPGA-based development kits that include boards with industrial peripherals such as 10/100 Ethernet, CAN, LIN, RS485, and other interfaces along with the needed FPGA design tools and software compilers to develop specific source code. Some kits also include embedded processors and peripheral IP that can be used for actual development.

Various members of the technical staff in the Industrial/Broadbase business unit of Altera Corp. contributed to this article.

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